In many electronic devices, for example memory devices, components may be clocked by an external clock signal and may perform operations at predetermined times relative to the rising and falling edges of the applied clock signal. Examples of synchronous integrated circuits include synchronous memory devices such as synchronous dynamic random access memories (“SDRAMs”), synchronous static random access memories (“SSRAMs”), and packetized memories like SLDRAMs and RDRAMs, and include other types of integrated circuits as well, such as microprocessors. The timing of signals external to a synchronous integrated circuit may be determined by an external clock signal, and operations within the synchronous integrated circuit may be synchronized to external operations. For example, commands may be placed on a command bus of a memory device in synchronism with an external clock signal, and the memory device may latch these commands at the proper times to successfully capture the commands. To latch the applied commands, an internal clock signal may be developed in response to the external clock signal, and is typically applied to latches contained in the memory device to clock the commands into the latches. The internal clock signal and external clock should be synchronized to ensure the internal clock signal clocks the latches at the proper times to successfully capture the commands. In the present description, “external” may refer to signals and operations outside of the memory device, and “internal” may refer to signals and operations within the memory device. Moreover, although the present description includes description of synchronous memory devices, the principles described herein are equally applicable to other types of synchronous integrated circuits or to the synchronization of generally any periodic signals.
To synchronize external and internal clock signals in modern synchronous memory devices, a number of different approaches have been considered and utilized, including delay locked loops (“DLLs”), as will be appreciated by those skilled in the art. Generally, these approaches utilize a delay line containing one or more delay elements to delay an input periodic signal and feed back a phase difference-related signal between the input and the output to control the amount of delay provided by the delay line. In this manner the output periodic signal may be “locked” to the input periodic signal.
FIG. 1 is a schematic illustration of a general delay locked loop 100. An input signal 105, Sig_in, may be provided to a buffer 107 which may generate the buffered signal Sig_buff 109. The buffered signal may be provided to a delay line 110 that is configured to delay the buffered signal in accordance with a control signal sig_cntrl 112 to generate an output signal, sig_out 114. To generate the control signal 112, a phase detector 120 and control logic 125 may be provided. The phase detector 120 may compare a phase of the output signal sig_out 114 with that of the buffered input signal sig_buff 109. The phase detector 120 may generate a signal corresponding to a phase difference between sig_buff 109 and sig_out 114. The signal corresponding to the phase difference ma be provided to the control logic 125, which may include, for example, a charge pump and/or a loop filter, which may in turn generate the control signal sig_contrl 112. Although not shown in FIG. 1, additional components such as multiple delay lines (for example, a coarse and fine delay line), or mock delays in the feedback path may also be included.
As speeds of electronic devices continue to increase, timing requirements for DLLs such as those shown in FIG. 1 are increasing. Jitter and/or skew may be caused by variations in the power supply voltage(s) which power the elements in the delay line 110. Voltage regulators may be used in an effort to maintain a constant power supply voltage and reduce or eliminate jitter or skew caused by power supply voltage variations.
Power supply voltages, however, are also decreasing in many electronic devices. It may be infeasible to continue to use voltage regulators to maintain constant power supply voltages at lower voltages.
Generally, the delay line 110, phase detector 120, and control logic 125 may be implemented using digital circuitry. For example, the delay line 110 may include multiple individual delay elements (e.g. stages) coupled in series, with each individual delay element delaying the input signal an amount and providing the delayed input signal to the next element, until the output signal sig_out 114 is generated. Each delay element is typically implemented using two NAND gates. The control logic 125 is typically configured to provide a digital signal to the delay line 110. That is, the sig_cntrl 112 is typically a digital signal.
Analog delay elements have been considered for use in the delay line 110; however, analog delay elements typically consume a larger area and more power than their digital counterparts.